USC Viterbi School of Engineering and Industrial Technology Research Institute to Collaborate on Microelectronics – USC Viterbi

The University of Southern California (USC) and the Industrial Technology Research Institute (ITRI) in Taiwan announced their collaboration to advance the field of microelectronics with a focus on research and development, design integrated circuits and manufacturing.

USC’s Ming Hsieh Department of Electrical and Computer Engineering (ECE), USC’s Institute for Information Science (ISI), and ITRI will collaborate on semiconductor research and development in fields of heterogeneous integration, artificial intelligence, non-volatile memory, next-generation computing and integrated circuits. Design. USC’s Metal Oxide Semiconductor Implementation Service (the MOSIS Service) and ITRI will focus on IC Design and Development Service, IP Support, and Silicon Shuttle Service. This coordinated research initiative is essential given the growing global demand for chips.

“ITRI does world-class research and their goal is to market, to get their products into major retail stores. Out of all the companies they could have worked with, they chose ISI because we are leading the industry and our team is doing a solid job,” said Lifu Chang, MOSIS Service Manager at ISI.

Yannis C. Yortsos, Dean of the USC Viterbi School of Engineering, said, “We are thrilled that USC’s ECE and ISI research teams with strong backgrounds in artificial intelligence, radio frequency and millimeter wave integrated circuit designs, analog IP, quantum computing and optoelectronics can expand their global collaborations with the outstanding teams at ITRI. We look forward to seeing how this R&D collaboration will advance microelectronics technologies into big innovation applications.

USC has a long history of expertise in chip design and security. At ISI, the MOSIS service was founded in 1981 at the USC Information Sciences Institute through a DARPA contract to facilitate early manufacturing projects for fabless organizations. After pioneering the Multi-Project Wafer (MPW) model, MOSIS has also provided services to US government laboratories, foreign and domestic corporations, and foreign and domestic universities.

“We are pioneers in the manufacture of microchips. We have three main categories of customers,” explains Chang. “Defense industry organizations, which are our very long-standing customers. Then the university community; almost all Americans have worked with us: UCLA, UC Berkeley, Stanford, MIT, etc. Then we work with commercial design companies. For example, we plan to sign an agreement with a company in San Diego, California to supply chips for their important medical applications.

Craig Knoblock, executive director of the Keston Institute for Information Science and associate dean of the USC Viterbi School of Engineering, said, “We are very encouraged by this opportunity to collaborate with ITRI. The MOSIS service has the state-of-the-art capabilities to support semiconductor design and manufacturing and we are now beginning to work with ITRI’s targeted IP development and silicon manufacturing platform. We look forward to seeing semiconductor projects come to fruition that will benefit innovative start-ups in the United States and Taiwan. »

ITRI ​​President Edwin Liu expressed his excitement to see how the partnership will bring new opportunities, using ITRI’s multidisciplinary R&D platforms and MOSIS’s prototyping capabilities. “ITRI and USC will collaborate through an institution-to-institution mechanism and create a customer service business model that will provide Taiwanese companies with chip packaging and related downstream services after trial production,” he said. .

Over the years, MOSIS has delivered chips for more than 60,000 designs and enabled IC designers to prototype innovative semiconductor designs. The Ming Hsieh department has provided expertise in materials and chip design for a wide variety of applications, with a recent focus on neural network and quantum computing design. Additionally, USC researchers have developed new methods to test chip integrity.

Posted on February 2, 2022

Last updated on February 2, 2022